The present invention relates to a semiconductor storage device, and particularly to a semiconductor storage device which stores data using magnetoresistive elements.
In recent years, non-volatile memories such as FLASH memories which do not require electric power to retain stored data are often mounted on mobile terminals or the like in place of volatile memories such as SRAMs (Static Random Access Memory) or DRAMs (Dynamic Random Access Memory) which require electric power to retain the stored data, in order to reduce power consumption.
However, it is time consuming to rewrite data stored in FLASH memories, and thus it has been difficult to write data therein at a high speed. Accordingly, MRAMs (Magneto resistive Random Access Memory) which allows rewriting of stored data in a short time are expected as a substitution of FLASH memories.
An MRAM, having a tunnel magnetoresistive element in a plurality of memory cells arranged in a matrix, stores data utilizing variation of a resistance value of the tunnel magnetoresistive element. However, the magnetoresistance ratio (MR ratio, (maximum resistance value−minimum resistance value)/minimum resistance value) of a tunnel magnetoresistive element is about 100% to 70% at most according to current technology, and thus the difference between the maximum resistance value storing the state of data “1” and the minimum resistance value storing the state of data “0” is small, which leads to a problem that data cannot be stably read by reading stored data using only the resistance value.
Therefore, with the MRAM disclosed in Japanese Patent Laid-Open No. 2005-209245 (Patent Document 1) and Japanese Patent Laid-Open No. 2005-069744 (Patent Document 2), the resistance value of the stored data is read by a current sense amplifier using a reference current generated by a combined resistance of the maximum resistance value storing the state of data “1” and the minimum resistance value storing the state of data “0”. Accordingly, with the MRAM disclosed in Patent Document 1 and Patent Document 2, a reference current generation circuit which generate a reference current, and a highly precise read amplifier circuit which can detect a minute current are required. In addition, as the MRAM disclosed in Japanese Patent Laid-Open No. 2004-039150 (Patent Document 3), an additional configuration is required to prevent erroneous reading of data due to parasitic current or noise.
Furthermore, with the MRAM disclosed in Japanese Patent Laid-Open No. 2004-220759 (Patent Document 4), a configuration for reading stored data without using a reference current is disclosed. However, with the MRAM disclosed in the Patent Document 4, a special read amplifier circuit which can amplify intermediate voltage of a signal of a read-bit-line to prevent the amplitude of the signal from becoming the maximum amplitude is required.